The design and performance of diferent nanoelectronic binary multipliers

Abstract

Abstract The design and performance of digital binary multipliers built using diferent types of nanoelectronic devices are investigated herein. Designs for 2 × 2 binary multipliers implemented using diferent technologies such as single-electron-threshold

logic (SE-TLG), hybrid single-electron transistor/complementary metal–oxide–semiconductor (SET-CMOS), and carbon

nanotube ield-efect transistor (CNFET) devices are elaborated and presented with corresponding simulation results. The

performance metrics considered for their comparison are the power consumption, the circuit area, the propagation delay, the

operating temperature, the design platform, etc. The existing CMOS-based design is also compared with all three proposed

designs. The comparative analysis indicates that the SE-TLG-based 2 × 2 binary multiplier design exhibits very low power

consumption, the smallest area requirement, and the shortest propagation delay among the three. Meanwhile, the design based

on hybrid SET-CMOS devices can operate at room temperature and delivers the optimal response in terms of all the other

performance metrics when compared with the other circuit implementations considered herein. Further stability analysis of

the designs based on SE-TLG and hybrid SET-CMOS devices is carried out to validate their performance.